Operation of JFET

OPERATION OF JFET

Case (i): When V_G applied and V_b = 0

Consider an N-channel JFET circuit as shown in fig.3.60. The P type gate and N-type channel constitute PN junction. This PN junction is always reverse biased in JFET operation.

The reverse bias is applied by a voltage source V_G connected between the gate and the source terminal. The positive terminal is connected to the source (S) and negative terminal to the gate (G).

When a PN junction is reverse biased, the electrons and holes diffuse across the junction and leave behind the positive ions on N. side and negative ions on P side. The region containing these immobile ions, is known as depletion region.

If both 'P' and 'N' regions heavily doped, then depletion region extend symmetrically on both sides. But in N-channel JFET, 'P' region is heavily doped than N type channel thus, depletion region extents more in N region than in 'P' region.

When no V_G is applied, the depletion region is a symmetrical and the conductivity becomes zero, since there are no mobile carriers in the junction. As the reverse bias voltage across the junction is increased, thickness of the depletion region also increases.

Case (ii): When V_G = 0 and V_DD is applied

When no voltage is applied to gate V_G = 0 and V_DD is applied between source and drain. The electron will flow from source to drain through the channel, constituting drain current I_D.

The channel resistance are represented as r_d and r_s as shown in fig.3.61 and its magnitude depends on V_DD and V_G.

The drain current I_D produces a voltage drop across r_d which reverse biases the gate to source junction, thus the depletion region formed which is not symmetrical. It penetrates deeper on to channel near drain and less to the source because Vr_d >> V_rs. So reverse bias is higher near drain than compared to source.

Case (iii): When V_DD and V_G is applied voltage

When voltage is applied between the drain and source with a supply of V the electrons flow from source to drain through the narrow channel existing between the depletion region. This constitutes the drain current (I_D), its conventional direction is indicated from drain to source.

The value of drain current is maximum, when no external voltage is applied between the gate and source and is designated by symbol I_DSS. When (V_GS or V_GG) gate to source voltage is increased beyond zero, the depletion regions are widened. This reduces the effective width of the channel and therefore control the flow of drain current through the channel.

When the gate to source voltage (V_GS) is increased further, a stage is reached at which two depletion regions touch each other. It is called as "pinch off region". This reduces the drain current to zero. The gate to source voltage at which the drain current is zero is called "pinch off voltage" (V_P). The value of pinch off voltage is negative for N channel JFET. It depends on, the doping of the N and P region of the device and the width of the channel.